This invention generally relates to burn-in. More particularly, it relates to test circuits on a wafer that permit reduced pin-count testing and burning-in of chips on the wafer. It also relates to a structure that provides for connecting good chips and disconnecting shorted chips.
Testing a large number of integrated circuit chips in parallel at the wafer level provides significant advantage since test time and cost are substantially reduced. At present, large scale testers including mainframe computers are needed to test even one chip at a time, and the complexity of these machines is increased when the capability of testing arrays of chips in parallel is added. Nevertheless, because of the time savings parallel testing provides, high pin-count testers capable of probing and collecting data from many chips simultaneously have been introduced, and the number of chips that can be tested simultaneously has been gradually increasing.
Wafer level burn-in adds to the difficulty and cost of simultaneous testing since the high pin-count probes must be kept in place on each wafer for many hours and the probes must maintain contact as temperature changes from room temperature to about 140xc2x0 C. In addition, a scheme to disconnect or limit current to shorted chips is needed to maintain voltage uniformity across the wafer.
Commonly assigned U.S. Pat. No. 5,600,257, to Leas et al. teaches apparatus for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips. Glass ceramic has a thermal coefficient of expansion comparable to that of silicon, enabling probe contact as temperature varies. The test chips provide test patterns. Voltage regulators are on the test chips to provide a specified voltage to the product chips and to limit current to shorted chips. However, glass ceramic carriers large enough to accommodate 8 inch semiconductor wafers are very expensive.
xe2x80x9cKnown good die,xe2x80x9d chips that have been individually tested and burned-in after dicing from a wafer, are becoming increasingly available in the industry to provide for multi-chip modules and other applications where high reliability is needed. Burning-in individual chips after dicing avoids the difficulties of contacting and burning-in all chips on a wafer at once. However, there is a substantial cost to handling, aligning, and holding individual chips for burn-in stress over many hours as compared with testing and burning-in at the wafer level.
Substantial lower cost would result from an improved wafer burn-in scheme that permits parallel test and burn-in of the chips on a wafer before dicing without a costly glass ceramic interface, and this solution is provided by the following invention.
It is therefore an object of the present invention to provide a wafer having integrated circuit chips and at least one test engine.
It is another object of the present invention to provide a test engine on a wafer capable of providing test signals to a plurality of chips.
It is another object of the present invention to provide a test engine on a wafer capable of providing test signals for full functional testing.
It is another object of the present invention to provide a test engine on a wafer capable of providing test signals at high frequency for testing and burn-in.
It is another object of the present invention to provide a test engine on a wafer capable of being programmed so patterns generated by the test engine can be altered after fabrication of the test engine to characterize newly discovered defects.
It is another object of the present invention to provide circuits capable of efficiently allocating redundancy repair information so integrated circuit chips can be optimally repaired after test or after burn-in to provide a high wafer yield.
It is another object of the present invention to distribute test engine functions so that some test engine functions are central and shared among several chips on a wafer and others are specific for each chip and located on each chip on the wafer or in the adjacent kerf.
It is another object of the present invention to provide a test engine architecture that provides compare and redundancy allocation on each chip of the wafer or in an adjacent kerf while control and data are provided by a shared test engine or a plurality of shared test engines.
It is another object of the present invention to provide a flex wiring membrane on the wafer to distribute power, ground, and signals.
It is another object of the present invention that a flex wiring membrane on the wafer provides contact to test engines and chips on the wafer.
It is another object of the present invention that a flex wiring membrane on the wafer provides a chip level package.
It is another object of the present invention to reduce test and burn-in time.
It is a feature of the present invention that a flex wiring membrane on the wafer interconnects a plurality of chips with a test engine.
It is an advantage of the present invention that a large number of chips on a wafer can be tested in parallel and burned-in with a low-cost tester and a low cost prober.
It is a feature of the present invention that a flex wiring membrane on the wafer provides a way to connect good chips and disconnect shorted chips.
It is an advantage of the present invention that the high speed signals provided by on-wafer test engines allow DRAM chips to be burned-in in a time shorter than is available with conventional burn-in ovens.
These and other objects, features, and advantages of the invention are accomplished by a semiconductor structure comprising a wafer and a membrane, the wafer having integrated circuit chips. The membrane comprises wiring. The wiring comprises first contacts that electrically connect the wiring to at least one of the chips. The wiring further comprises second contacts for connecting the wiring to a next level of assembly after the chips and a corresponding portion of the membrane are diced.
Another aspect of the invention is a semiconductor structure, comprising a wafer including integrated circuit chips that have memory arrays. The wafer has a circuit comprising a first element, a second element, and a third element. The first element is capable of presenting array test patterns to the memory array. The second element is capable of receiving a result of the test patterns from the array. The third element is capable of using the result to allocate redundancy to repair a defect on the memory array. The structure includes contacts for electrically connecting the circuit for external electrical connection for testing or burning-in the array at wafer level.
Another aspect of the invention is a semiconductor structure comprising a wafer having a plurality of integrated circuit chips and a test engine, the test engine connected to the plurality of chips. Thus, the chips share a test engine.
Another aspect of the invention is a semiconductor structure comprising a wafer having a plurality of integrated circuit chips and a contactor physically connected to the chips. The contactor has selectable contacts to form or break electrical connection to selected chips while maintaining the physical connection.